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46adbbb3b2
* Loop-based impl * Add asserts * Add another test case * Update StructWithGC_Zeroing.csproj * Update StructWithGC_Zeroing.cs * clean up * Fix arm32 * Address feedback * Add a small note * Add RISC-V and LA64 * Address feedback * fix build * fix build * CI test * Fix build * Clean up * Apply suggestion * Use REG_R0 on RISC-V and LA64, use ZR on ARM64 * fix build * Clean up * Update src/coreclr/jit/codegenloongarch64.cpp Co-authored-by: Qiao Pengcheng <qiaopengcheng@loongson.cn> * Apply suggestions for risc-v --------- Co-authored-by: EgorBo <egorbo@gmail.com> Co-authored-by: Qiao Pengcheng <qiaopengcheng@loongson.cn> |
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