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[LoongArch64] Initial DFEATURE_EMULATE_SINGLESTEP for LA64. (#105741)
This commit is contained in:
Xu Liangyu
parent
b284b1c082
commit
e3684bce47
GPG key ID:
B5690EEEBB952194
9 changed files with 620 additions and 20 deletions
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@ -28,6 +28,8 @@ if (CLR_CMAKE_TARGET_UNIX)
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add_compile_definitions($<$<NOT:$<BOOL:$<TARGET_PROPERTY:IGNORE_DEFAULT_TARGET_ARCH>>>:UNIX_ARM_ABI>)
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elseif (CLR_CMAKE_TARGET_ARCH_I386)
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add_compile_definitions($<$<NOT:$<BOOL:$<TARGET_PROPERTY:IGNORE_DEFAULT_TARGET_ARCH>>>:UNIX_X86_ABI>)
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elseif (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
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add_definitions(-DFEATURE_EMULATE_SINGLESTEP)
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endif()
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endif(CLR_CMAKE_TARGET_UNIX)
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@ -3202,7 +3202,7 @@ void DebuggerController::ApplyTraceFlag(Thread *thread)
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g_pEEInterface->MarkThreadForDebugStepping(thread, true);
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LOG((LF_CORDB,LL_INFO1000, "DC::ApplyTraceFlag marked thread for debug stepping\n"));
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SetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread));
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SetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread) LOONGARCH64_ARG(thread));
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}
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//
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@ -3239,7 +3239,7 @@ void DebuggerController::UnapplyTraceFlag(Thread *thread)
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// Always need to unmark for stepping
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g_pEEInterface->MarkThreadForDebugStepping(thread, false);
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UnsetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread));
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UnsetSSFlag(reinterpret_cast<DT_CONTEXT *>(context) ARM_ARG(thread) ARM64_ARG(thread) RISCV64_ARG(thread) LOONGARCH64_ARG(thread));
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}
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void DebuggerController::EnableExceptionHook()
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@ -15890,7 +15890,7 @@ BOOL Debugger::IsThreadContextInvalid(Thread *pThread, CONTEXT *pCtx)
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if (success)
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{
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// Check single-step flag
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if (IsSSFlagEnabled(reinterpret_cast<DT_CONTEXT *>(pCtx) ARM_ARG(pThread) ARM64_ARG(pThread) RISCV64_ARG(pThread)))
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if (IsSSFlagEnabled(reinterpret_cast<DT_CONTEXT *>(pCtx) ARM_ARG(pThread) ARM64_ARG(pThread) RISCV64_ARG(pThread) LOONGARCH64_ARG(pThread)))
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{
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// Can't hijack a thread whose SS-flag is set. This could lead to races
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// with the thread taking the SS-exception.
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@ -10,3 +10,25 @@ void CopyREGDISPLAY(REGDISPLAY* pDst, REGDISPLAY* pSrc)
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CONTEXT tmp;
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CopyRegDisplay(pSrc, pDst, &tmp);
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}
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void SetSSFlag(DT_CONTEXT *, Thread *pThread)
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{
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_ASSERTE(pThread != NULL);
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pThread->EnableSingleStep();
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}
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void UnsetSSFlag(DT_CONTEXT *, Thread *pThread)
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{
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_ASSERTE(pThread != NULL);
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pThread->DisableSingleStep();
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}
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// Check if single stepping is enabled.
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bool IsSSFlagEnabled(DT_CONTEXT *, Thread *pThread)
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{
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_ASSERTE(pThread != NULL);
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return pThread->IsSingleStepEnabled();
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}
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@ -219,24 +219,15 @@ inline bool AddressIsBreakpoint(CORDB_ADDRESS_TYPE* address)
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return CORDbgGetInstruction(address) == CORDbg_BREAK_INSTRUCTION;
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}
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inline void SetSSFlag(DT_CONTEXT *pContext)
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{
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// TODO-LoongArch64: LoongArch64 doesn't support cpsr.
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_ASSERTE(!"unimplemented on LOONGARCH64 yet");
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}
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class Thread;
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// Enable single stepping.
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void SetSSFlag(DT_CONTEXT *pCtx, Thread *pThread);
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inline void UnsetSSFlag(DT_CONTEXT *pContext)
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{
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// TODO-LoongArch64: LoongArch64 doesn't support cpsr.
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_ASSERTE(!"unimplemented on LOONGARCH64 yet");
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}
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// Disable single stepping
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void UnsetSSFlag(DT_CONTEXT *pCtx, Thread *pThread);
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inline bool IsSSFlagEnabled(DT_CONTEXT * pContext)
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{
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// TODO-LoongArch64: LoongArch64 doesn't support cpsr.
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_ASSERTE(!"unimplemented on LOONGARCH64 yet");
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return false;
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}
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// Check if single stepping is enabled.
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bool IsSSFlagEnabled(DT_CONTEXT *pCtx, Thread *pThread);
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inline bool PRDIsEqual(PRD_TYPE p1, PRD_TYPE p2)
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@ -842,6 +842,7 @@ elseif(CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
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set(VM_SOURCES_WKS_ARCH
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${ARCH_SOURCES_DIR}/profiler.cpp
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${ARCH_SOURCES_DIR}/singlestepper.cpp
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gcinfodecoder.cpp
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)
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elseif(CLR_CMAKE_TARGET_ARCH_RISCV64)
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492
src/coreclr/vm/loongarch64/singlestepper.cpp
Normal file
492
src/coreclr/vm/loongarch64/singlestepper.cpp
Normal file
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@ -0,0 +1,492 @@
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// Licensed to the .NET Foundation under one or more agreements.
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// The .NET Foundation licenses this file to you under the MIT license.
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//
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//
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// Emulate hardware single-step on LOONGARCH64.
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//
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#include "common.h"
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#include "loongarch64singlestepper.h"
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inline uint64_t SignExtend(uint64_t value, unsigned int signbit)
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{
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_ASSERTE(signbit < 64);
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if (signbit == 63)
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return value;
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uint64_t sign = value & (1ull << signbit);
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if (sign)
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return value | (~0ull << signbit);
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else
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return value;
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}
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inline uint64_t BitExtract(uint64_t value, unsigned int highbit, unsigned int lowbit, bool signExtend = false)
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{
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_ASSERTE((highbit < 64) && (lowbit < 64) && (highbit >= lowbit));
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uint64_t extractedValue = (value >> lowbit) & ((1ull << ((highbit - lowbit) + 1)) - 1);
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return signExtend ? SignExtend(extractedValue, highbit - lowbit) : extractedValue;
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}
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//
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// LoongArch64SingleStepper methods.
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//
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LoongArch64SingleStepper::LoongArch64SingleStepper()
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: m_originalPc(0), m_targetPc(0), m_rgCode(0), m_state(Disabled),
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m_fEmulate(false), m_fBypass(false)
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{
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m_opcodes[0] = 0;
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}
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LoongArch64SingleStepper::~LoongArch64SingleStepper()
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{
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#if !defined(DACCESS_COMPILE)
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SystemDomain::GetGlobalLoaderAllocator()->GetExecutableHeap()->BackoutMem(m_rgCode, kMaxCodeBuffer * sizeof(uint32_t));
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#endif
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}
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void LoongArch64SingleStepper::Init()
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{
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#if !defined(DACCESS_COMPILE)
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if (m_rgCode == NULL)
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{
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m_rgCode = (uint32_t *)(void *)SystemDomain::GetGlobalLoaderAllocator()->GetExecutableHeap()->AllocMem(S_SIZE_T(kMaxCodeBuffer * sizeof(uint32_t)));
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}
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#endif
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}
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// Given the context with which a thread will be resumed, modify that context such that resuming the thread
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// will execute a single instruction before raising an EXCEPTION_BREAKPOINT. The thread context must be
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// cleaned up via the Fixup method below before any further exception processing can occur (at which point the
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// caller can behave as though EXCEPTION_SINGLE_STEP was raised).
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void LoongArch64SingleStepper::Enable()
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{
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_ASSERTE(m_state != Applied);
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if (m_state == Enabled)
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{
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// We allow single-stepping to be enabled multiple times before the thread is resumed, but we require
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// that the thread state is the same in all cases (i.e. additional step requests are treated as
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// no-ops).
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_ASSERTE(!m_fBypass);
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_ASSERTE(m_opcodes[0] == 0);
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return;
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}
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Enable\n"));
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m_fBypass = false;
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m_opcodes[0] = 0;
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m_state = Enabled;
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}
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void LoongArch64SingleStepper::Bypass(uint64_t ip, uint32_t opcode)
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{
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_ASSERTE(m_state != Applied);
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if (m_state == Enabled)
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{
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// We allow single-stepping to be enabled multiple times before the thread is resumed, but we require
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// that the thread state is the same in all cases (i.e. additional step requests are treated as
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// no-ops).
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if (m_fBypass)
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{
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_ASSERTE(m_opcodes[0] == opcode);
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_ASSERTE(m_originalPc == ip);
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return;
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}
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}
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Bypass(pc=%lx, opcode=%x)\n", ip, opcode));
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m_fBypass = true;
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m_originalPc = ip;
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m_opcodes[0] = opcode;
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m_state = Enabled;
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}
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void LoongArch64SingleStepper::Apply(T_CONTEXT *pCtx)
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{
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if (m_rgCode == NULL)
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{
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Init();
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// OOM. We will simply ignore the single step.
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if (m_rgCode == NULL)
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return;
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}
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_ASSERTE(pCtx != NULL);
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if (!m_fBypass)
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{
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uint64_t pc = pCtx->Pc;
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m_opcodes[0] = *(uint32_t*)pc; // Opcodes are always in little endian, we only support little endian execution mode
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}
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uint32_t opcode = m_opcodes[0];
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Apply(pc=%lx, opcode=%x)\n", (uint64_t)pCtx->Pc, opcode));
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#ifdef _DEBUG
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// Make sure that we aren't trying to step through our own buffer. If this asserts, something is horribly
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// wrong with the debugging layer. Likely GetManagedStoppedCtx is retrieving a Pc that points to our
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// buffer, even though the single stepper is disabled.
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uint64_t codestart = (uint64_t)m_rgCode;
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uint64_t codeend = codestart + (kMaxCodeBuffer * sizeof(uint32_t));
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_ASSERTE((pCtx->Pc < codestart) || (pCtx->Pc >= codeend));
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#endif
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// All stepping is simulated using a breakpoint instruction. Since other threads are not suspended while
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// we step, we avoid race conditions and other complexity by redirecting the thread into a thread-local
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// execution buffer. We can either copy the instruction we wish to step over into the buffer followed by a
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// breakpoint or we can emulate the instruction (which is useful for instruction that depend on the value
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// of the PC or that branch or call to an alternate location). Even in the emulation case we still
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// redirect execution into the buffer and insert a breakpoint; this simplifies our interface since the
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// rest of the runtime is not set up to expect single stepping to occur inline. Instead there is always a
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// 1:1 relationship between setting the single-step mode and receiving an exception once the thread is
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// restarted.
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//
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// There are two parts to the emulation:
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// 1) In this method we either emulate the instruction (updating the input thread context as a result) or
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// copy the single instruction into the execution buffer. In both cases we copy a breakpoint into the
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// execution buffer as well then update the thread context to redirect execution into this buffer.
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// 2) In the runtime's first chance vectored exception handler we perform the necessary fixups to make
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// the exception look like the result of a single step. This includes resetting the PC to its correct
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// value (either the instruction following the stepped instruction or the target PC cached in this
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// object when we emulated an instruction that alters the PC). It also involves switching
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// EXCEPTION_BREAKPOINT to EXCEPTION_SINGLE_STEP.
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//
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// If we encounter an exception while emulating an instruction (currently this can only happen if we A/V
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// trying to read a value from memory) then we abandon emulation and fall back to the copy instruction
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// mechanism. When we run the execution buffer the exception should be raised and handled as normal (we
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// still perform context fixup in this case but we don't attempt to alter any exception code other than
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// EXCEPTION_BREAKPOINT to EXCEPTION_SINGLE_STEP). There is a very small timing window here where another
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// thread could alter memory protections to avoid the A/V when we run the instruction for real but the
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// liklihood of this happening (in managed code no less) is judged sufficiently small that it's not worth
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// the alternate solution (where we'd have to set the thread up to raise an exception with exactly the
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// right thread context).
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// Cache thread's initial PC since we'll overwrite them as part of the emulation and we need
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// to get back to the correct values at fixup time. We also cache a target PC (set below) since some
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// instructions will set the PC directly or otherwise make it difficult for us to compute the final PC
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// from the original. We still need the original PC however since this is the one we'll use if an
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// exception (other than a breakpoint) occurs.
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_ASSERTE((!m_fBypass || (m_originalPc == pCtx->Pc)));
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m_originalPc = pCtx->Pc;
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// By default assume the next PC is right after the current instruction.
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m_targetPc = m_originalPc + sizeof(uint32_t);
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m_fEmulate = false;
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// There are two different scenarios we must deal with (listed in priority order). In all cases we will
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// redirect the thread to execute code from our buffer and end by raising a breakpoint exception:
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// 1) The current instruction either takes the PC as an input or modifies the PC.
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// We can't easily run these instructions from the redirect buffer so we emulate their effect (i.e.
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// update the current context in the same way as executing the instruction would). The breakpoint
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// fixup logic will restore the PC to the real resultant PC we cache in m_targetPc.
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// 2) For all other cases (including emulation cases where we aborted due to a memory fault) we copy the
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// single instruction into the redirect buffer for execution followed by a breakpoint (once we regain
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// control in the breakpoint fixup logic we can then reset the PC to its proper location.
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unsigned int idxNextInstruction = 0;
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ExecutableWriterHolder<DWORD> codeWriterHolder(m_rgCode, kMaxCodeBuffer * sizeof(m_rgCode[0]));
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if (TryEmulate(pCtx, opcode, false))
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{
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper: Case 1: Emulate\n"));
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// Case 1: Emulate an instruction that reads or writes the PC.
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m_fEmulate = true;
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}
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else
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{
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper: Case 2: CopyInstruction.\n"));
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// Case 2: In all other cases copy the instruction to the buffer and we'll run it directly.
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codeWriterHolder.GetRW()[idxNextInstruction++] = opcode;
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}
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// Always terminate the redirection buffer with a breakpoint.
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codeWriterHolder.GetRW()[idxNextInstruction++] = kBreakpointOp;
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_ASSERTE(idxNextInstruction <= kMaxCodeBuffer);
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// Set the thread up so it will redirect to our buffer when execution resumes.
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pCtx->Pc = (uint64_t)m_rgCode;
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// Make sure the CPU sees the updated contents of the buffer.
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FlushInstructionCache(GetCurrentProcess(), m_rgCode, kMaxCodeBuffer * sizeof(m_rgCode[0]));
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// Done, set the state.
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m_state = Applied;
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}
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void LoongArch64SingleStepper::Disable()
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{
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_ASSERTE(m_state != Applied);
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m_state = Disabled;
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}
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// When called in response to an exception (preferably in a first chance vectored handler before anyone else
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// has looked at the thread context) this method will (a) determine whether this exception was raised by a
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// call to Enable() above, in which case true will be returned and (b) perform final fixup of the thread
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// context passed in to complete the emulation of a hardware single step. Note that this routine must be
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// called even if the exception code is not EXCEPTION_BREAKPOINT since the instruction stepped might have
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// raised its own exception (e.g. A/V) and we still need to fix the thread context in this case.
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bool LoongArch64SingleStepper::Fixup(T_CONTEXT *pCtx, DWORD dwExceptionCode)
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{
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#ifdef _DEBUG
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uint64_t codestart = (uint64_t)m_rgCode;
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uint64_t codeend = codestart + (kMaxCodeBuffer * sizeof(uint32_t));
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#endif
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// If we reach fixup, we should either be Disabled or Applied. If we reach here with Enabled it means
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// that the debugging layer Enabled the single stepper, but we never applied it to a CONTEXT.
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_ASSERTE(m_state != Enabled);
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// Nothing to do if the stepper is disabled on this thread.
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if (m_state == Disabled)
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{
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// We better not be inside our internal code buffer though.
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_ASSERTE((pCtx->Pc < codestart) || (pCtx->Pc > codeend));
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return false;
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}
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// Turn off the single stepper after we have executed one instruction.
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m_state = Disabled;
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// We should always have a PC somewhere in our redirect buffer.
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#ifdef _DEBUG
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_ASSERTE((pCtx->Pc >= codestart) && (pCtx->Pc <= codeend));
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#endif
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if (dwExceptionCode == EXCEPTION_BREAKPOINT)
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{
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// The single step went as planned. Set the PC back to its real value (either following the
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// instruction we stepped or the computed destination we cached after emulating an instruction that
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// modifies the PC).
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if (!m_fEmulate)
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{
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if (m_rgCode[0] != kBreakpointOp)
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{
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Fixup executed code, ip = %lx\n", m_targetPc));
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pCtx->Pc = m_targetPc;
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}
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else
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{
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// We've hit a breakpoint in the code stream. We will return false here (which causes us to NOT
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// replace the breakpoint code with single step), and place the Pc back to the original Pc. The
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// debugger patch skipping code will move past this breakpoint.
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LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Fixup emulated breakpoint\n"));
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pCtx->Pc = m_originalPc;
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_ASSERTE((pCtx->Pc & 0x3) == 0);
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return false;
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}
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}
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else
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{
|
||||
bool res = TryEmulate(pCtx, m_opcodes[0], true);
|
||||
_ASSERTE(res); // We should always successfully emulate since we ran it through TryEmulate already.
|
||||
|
||||
pCtx->Pc = m_targetPc;
|
||||
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Fixup emulated, ip = %lx\n", pCtx->Pc));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// The stepped instruction caused an exception. Reset the PC to its original values we
|
||||
// cached before stepping.
|
||||
_ASSERTE(m_fEmulate == false);
|
||||
pCtx->Pc = m_originalPc;
|
||||
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::Fixup hit exception pc = %lx ex = %x\n", pCtx->Pc, dwExceptionCode));
|
||||
}
|
||||
|
||||
_ASSERTE((pCtx->Pc & 0x3) == 0);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Get the current value of a register.
|
||||
uint64_t LoongArch64SingleStepper::GetReg(T_CONTEXT *pCtx, uint64_t reg)
|
||||
{
|
||||
_ASSERTE(reg <= 31);
|
||||
_ASSERTE(pCtx->R0 == 0);
|
||||
|
||||
return (&pCtx->R0)[reg];
|
||||
}
|
||||
|
||||
// Set the current value of a register.
|
||||
void LoongArch64SingleStepper::SetReg(T_CONTEXT *pCtx, uint64_t reg, uint64_t value)
|
||||
{
|
||||
_ASSERTE(reg <= 31);
|
||||
|
||||
if (reg != 0) // Do nothing for R0, register R0 is hardwired to the constant 0.
|
||||
(&pCtx->R0)[reg] = value;
|
||||
}
|
||||
|
||||
// Parse the instruction opcode. If the instruction reads or writes the PC it will be emulated by updating
|
||||
// the thread context appropriately and true will be returned. If the instruction is not one of those cases
|
||||
// (or it is but we faulted trying to read memory during the emulation) no state is updated and false is
|
||||
// returned instead.
|
||||
bool LoongArch64SingleStepper::TryEmulate(T_CONTEXT *pCtx, uint32_t opcode, bool execute)
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate(opcode=%x, execute=%s)\n", opcode, execute ? "true" : "false"));
|
||||
|
||||
// Track whether instruction emulation wrote a modified PC.
|
||||
bool fRedirectedPc = false;
|
||||
|
||||
// Track whether we successfully emulated an instruction. If we did and we didn't modify the PC (e.g. a
|
||||
// PCALAU12I instruction or a conditional branch not taken) then we'll need to explicitly set the PC to the next
|
||||
// instruction (since our caller expects that whenever we return true m_pCtx->Pc holds the next
|
||||
// instruction address).
|
||||
bool fEmulated = false;
|
||||
|
||||
uint32_t op = (opcode >> 26) & 0x3f;
|
||||
|
||||
if ((op == 0x6) || (op == 0x7)) // PC-Rel addressing (PCADDU12I, PCALAU12I, PCADDU18I)
|
||||
{
|
||||
fEmulated = true;
|
||||
if (execute)
|
||||
{
|
||||
uint64_t P = BitExtract(opcode, 25, 25);
|
||||
uint64_t imm = BitExtract(opcode, 24, 5, true);
|
||||
uint64_t Rd = BitExtract(opcode, 4, 0);
|
||||
|
||||
if ((op == 0x6) && P) // PCALAU12I
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate PCALAU12I\n"));
|
||||
uint64_t value = (m_originalPc & ~0xfffull) + (imm << 12);
|
||||
SetReg(pCtx, Rd, value);
|
||||
}
|
||||
else if (P)// PCADDU18I
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate PCADDU18I\n"));
|
||||
uint64_t value = m_originalPc + (imm << 18);
|
||||
SetReg(pCtx, Rd, value);
|
||||
}
|
||||
else // PCADDU12I
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate PCADDU12I\n"));
|
||||
uint64_t value = m_originalPc + (imm << 12);
|
||||
SetReg(pCtx, Rd, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((op == 0x16) || (op == 0x17) || (op == 0x18) || (op == 0x19) || (op == 0x1a) ||(op == 0x1b)) // B.cond: BEQ, BNE, BLT, BGE, BLTU, BGEU
|
||||
{
|
||||
fEmulated = true;
|
||||
if (execute)
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate B.cond: BEQ, BNE, BLT[U], BGE[U]\n"));
|
||||
uint64_t imm16 = BitExtract(opcode, 25, 10, true);
|
||||
uint64_t rd = BitExtract(opcode, 4, 0);
|
||||
uint64_t rj = BitExtract(opcode, 9, 5);
|
||||
|
||||
int64_t rdSValue = GetReg(pCtx, rd);
|
||||
int64_t rjSValue = GetReg(pCtx, rj);
|
||||
uint64_t rdUValue = GetReg(pCtx, rd);
|
||||
uint64_t rjUValue = GetReg(pCtx, rj);
|
||||
|
||||
if (((op == 0x16) && (rjSValue == rdSValue)) ||
|
||||
((op == 0x17) && (rjSValue != rdSValue)) ||
|
||||
((op == 0x18) && (rjSValue < rdSValue)) ||
|
||||
((op == 0x19) && (rjSValue >= rdSValue)) ||
|
||||
((op == 0x1a) && (rjUValue < rdUValue)) ||
|
||||
((op == 0x1b) && (rjUValue >= rdUValue)))
|
||||
{
|
||||
uint64_t imm = (imm16 << 2);
|
||||
fRedirectedPc = true;
|
||||
m_targetPc = m_originalPc + imm;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((op == 0x10) || (op == 0x11)) // Compare and branch BEQZ, BNEZ
|
||||
{
|
||||
fEmulated = true;
|
||||
if (execute)
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate BEQZ, BNEZ\n"));
|
||||
|
||||
uint64_t immlo = BitExtract(opcode, 25, 10);
|
||||
uint64_t immhi = BitExtract(opcode, 4, 0, true);
|
||||
uint64_t imm = ((immhi << 16) | immlo) << 2;
|
||||
|
||||
uint64_t rj = BitExtract(opcode, 9, 5);
|
||||
uint64_t rjValue = GetReg(pCtx, rj);
|
||||
|
||||
if (((op == 0x10) && (rjValue == 0)) ||
|
||||
((op == 0x11) && (rjValue != 0)))
|
||||
{
|
||||
fRedirectedPc = true;
|
||||
m_targetPc = m_originalPc + imm;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((op == 0x14) || (op == 0x15)) // Unconditional branch immediate (B, BL)
|
||||
{
|
||||
fEmulated = true;
|
||||
if (execute)
|
||||
{
|
||||
uint64_t immlo = BitExtract(opcode, 25, 10);
|
||||
uint64_t immhi = BitExtract(opcode, 9, 0, true);
|
||||
uint64_t imm = ((immhi << 16) | immlo) << 2;
|
||||
|
||||
fRedirectedPc = true;
|
||||
m_targetPc = m_originalPc + imm;
|
||||
|
||||
if (op == 0x14) //B
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate B\n"));
|
||||
}
|
||||
else // BL
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate BL\n"));
|
||||
SetReg(pCtx, 1, m_originalPc + 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (op == 0x13) // Unconditional branch register JIRL
|
||||
{
|
||||
fEmulated = true;
|
||||
if (execute)
|
||||
{
|
||||
int imm = (short)((opcode >> 10) & 0xffff);
|
||||
imm <<= 2;
|
||||
|
||||
uint64_t rd = BitExtract(opcode, 4, 0);
|
||||
uint64_t rj = BitExtract(opcode, 9, 5);
|
||||
|
||||
if (rd == 0) // JIRL 0, RJ
|
||||
{
|
||||
fRedirectedPc = true;
|
||||
m_targetPc = GetReg(pCtx, rj) + (int)imm;
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate JIRL 0 RA\n"));
|
||||
}
|
||||
else if (rd == 1) // JIRL RA, RJ
|
||||
{
|
||||
SetReg(pCtx, 1, m_originalPc + 4);
|
||||
fRedirectedPc = true;
|
||||
m_targetPc = GetReg(pCtx, rj) + (int)imm;
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate JIRL RA target\n"));
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate unexpected for JIRL !\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
LOG((LF_CORDB, LL_INFO100000, "LoongArch64SingleStepper::TryEmulate(opcode=%x) emulated=%s redirectedPc=%s\n",
|
||||
opcode, fEmulated ? "true" : "false", fRedirectedPc ? "true" : "false"));
|
||||
|
||||
return fEmulated;
|
||||
}
|
||||
87
src/coreclr/vm/loongarch64singlestepper.h
Normal file
87
src/coreclr/vm/loongarch64singlestepper.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
// Licensed to the .NET Foundation under one or more agreements.
|
||||
// The .NET Foundation licenses this file to you under the MIT license.
|
||||
//
|
||||
|
||||
//
|
||||
// Emulate hardware single-step on LOONGARCH64.
|
||||
//
|
||||
|
||||
#ifndef __LOONGARCH64_SINGLE_STEPPER_H__
|
||||
#define __LOONGARCH64_SINGLE_STEPPER_H__
|
||||
|
||||
// Class that encapsulates the context needed to single step one thread.
|
||||
class LoongArch64SingleStepper
|
||||
{
|
||||
public:
|
||||
LoongArch64SingleStepper();
|
||||
~LoongArch64SingleStepper();
|
||||
|
||||
// Given the context with which a thread will be resumed, modify that context such that resuming the
|
||||
// thread will execute a single instruction before raising an EXCEPTION_BREAKPOINT. The thread context
|
||||
// must be cleaned up via the Fixup method below before any further exception processing can occur (at
|
||||
// which point the caller can behave as though EXCEPTION_SINGLE_STEP was raised).
|
||||
void Enable();
|
||||
|
||||
void Bypass(uint64_t ip, uint32_t opcode);
|
||||
|
||||
void Apply(T_CONTEXT *pCtx);
|
||||
|
||||
// Disables the single stepper.
|
||||
void Disable();
|
||||
|
||||
// Returns whether or not the stepper is enabled.
|
||||
inline bool IsEnabled() const
|
||||
{
|
||||
return m_state == Enabled || m_state == Applied;
|
||||
}
|
||||
|
||||
// When called in response to an exception (preferably in a first chance vectored handler before anyone
|
||||
// else has looked at the thread context) this method will (a) determine whether this exception was raised
|
||||
// by a call to Enable() above, in which case true will be returned and (b) perform final fixup of the
|
||||
// thread context passed in to complete the emulation of a hardware single step. Note that this routine
|
||||
// must be called even if the exception code is not EXCEPTION_BREAKPOINT since the instruction stepped
|
||||
// might have raised its own exception (e.g. A/V) and we still need to fix the thread context in this
|
||||
// case.
|
||||
bool Fixup(T_CONTEXT *pCtx, DWORD dwExceptionCode);
|
||||
|
||||
private:
|
||||
enum
|
||||
{
|
||||
kMaxCodeBuffer = 2, // max slots in our redirect buffer
|
||||
// 1 for current instruction
|
||||
// 1 for final breakpoint
|
||||
|
||||
kBreakpointOp = 0x002A0005, // Opcode for the breakpoint instruction used on LoongArch64 Unix
|
||||
};
|
||||
|
||||
enum StepperState
|
||||
{
|
||||
Disabled,
|
||||
Enabled,
|
||||
Applied
|
||||
};
|
||||
|
||||
uint64_t m_originalPc; // PC value before stepping
|
||||
uint64_t m_targetPc; // Final PC value after stepping if no exception is raised
|
||||
uint32_t *m_rgCode; // Buffer execution is redirected to during the step
|
||||
StepperState m_state; // Tracks whether the stepper is Enabled, Disabled, or enabled and applied to a context
|
||||
uint32_t m_opcodes[1];
|
||||
bool m_fEmulate;
|
||||
bool m_fBypass;
|
||||
|
||||
// Initializes m_rgCode. Not thread safe.
|
||||
void Init();
|
||||
|
||||
// Get the current value of a register.
|
||||
uint64_t GetReg(T_CONTEXT *pCtx, uint64_t reg);
|
||||
// Set the current value of a register.
|
||||
void SetReg(T_CONTEXT *pCtx, uint64_t reg, uint64_t value);
|
||||
|
||||
// Parse the instruction opcode. If the instruction reads or writes the PC it will be emulated by updating
|
||||
// the thread context appropriately and true will be returned. If the instruction is not one of those cases
|
||||
// (or it is but we faulted trying to read memory during the emulation) no state is updated and false is
|
||||
// returned instead.
|
||||
bool TryEmulate(T_CONTEXT *pCtx, uint32_t opcode, bool execute);
|
||||
};
|
||||
|
||||
#endif // !__LOONGARCH64_SINGLE_STEPPER_H__
|
||||
|
|
@ -184,6 +184,9 @@ struct TailCallArgBuffer
|
|||
#if (defined(TARGET_RISCV64) && defined(FEATURE_EMULATE_SINGLESTEP))
|
||||
#include "riscv64singlestepper.h"
|
||||
#endif
|
||||
#if (defined(TARGET_LOONGARCH64) && defined(FEATURE_EMULATE_SINGLESTEP))
|
||||
#include "loongarch64singlestepper.h"
|
||||
#endif
|
||||
|
||||
#if !defined(PLATFORM_SUPPORTS_SAFE_THREADSUSPEND)
|
||||
// DISABLE_THREADSUSPEND controls whether Thread::SuspendThread will be used at all.
|
||||
|
|
@ -2085,6 +2088,8 @@ private:
|
|||
ArmSingleStepper m_singleStepper;
|
||||
#elif defined(TARGET_RISCV64)
|
||||
RiscV64SingleStepper m_singleStepper;
|
||||
#elif defined(TARGET_LOONGARCH64)
|
||||
LoongArch64SingleStepper m_singleStepper;
|
||||
#else
|
||||
Arm64SingleStepper m_singleStepper;
|
||||
#endif
|
||||
|
|
@ -2100,7 +2105,7 @@ public:
|
|||
m_singleStepper.Enable();
|
||||
}
|
||||
|
||||
void BypassWithSingleStep(const void* ip ARM_ARG(WORD opcode1) ARM_ARG(WORD opcode2) ARM64_ARG(uint32_t opcode) RISCV64_ARG(uint32_t opcode))
|
||||
void BypassWithSingleStep(const void* ip ARM_ARG(WORD opcode1) ARM_ARG(WORD opcode2) ARM64_ARG(uint32_t opcode) RISCV64_ARG(uint32_t opcode) LOONGARCH64_ARG(uint32_t opcode))
|
||||
{
|
||||
#if defined(TARGET_ARM)
|
||||
m_singleStepper.Bypass((DWORD)ip, opcode1, opcode2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue