VSadov/Satori
1
0
Fork 0
mirror of https://github.com/VSadov/Satori.git synced 2025-06-11 02:13:38 +09:00
Code Activity

Don't use ZR as target in LSE atomics (#105854)

Browse source 
* Don't use ZR as target in LSE atomics

* Update codegenarm64.cpp

* Update lsraarm64.cpp

* Update lsraarm64.cpp
This commit is contained in:
Egor Bogatov 2024-08-05 18:09:40 +02:00 • committed by GitHub
parent ab03e0ffc0
commit 53a500edf1
Signed by: github
GPG key ID: B5690EEEBB952194
2 changed files with 16 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

13
src/coreclr/jit/codegenarm64.cpp
View file

@ -3878,19 +3878,21 @@ void CodeGen::genLockedInstructions(GenTreeOp* treeNode)
{ {
assert(!data->isContainedIntOrIImmed()); assert(!data->isContainedIntOrIImmed());
// These instructions change semantics when targetReg is ZR (the memory ordering becomes weaker).
// See atomicBarrierDroppedOnZero in LLVM
assert((targetReg != REG_NA) && (targetReg != REG_ZR));
switch (treeNode->gtOper) switch (treeNode->gtOper)
{ {
case GT_XORR: case GT_XORR:
GetEmitter()->emitIns_R_R_R(INS_ldsetal, dataSize, dataReg, (targetReg == REG_NA) ? REG_ZR : targetReg, GetEmitter()->emitIns_R_R_R(INS_ldsetal, dataSize, dataReg, targetReg, addrReg);
addrReg);
break; break;
case GT_XAND: case GT_XAND:
{ {
// Grab a temp reg to perform `MVN` for dataReg first. // Grab a temp reg to perform `MVN` for dataReg first.
regNumber tempReg = internalRegisters.GetSingle(treeNode); regNumber tempReg = internalRegisters.GetSingle(treeNode);
GetEmitter()->emitIns_R_R(INS_mvn, dataSize, tempReg, dataReg); GetEmitter()->emitIns_R_R(INS_mvn, dataSize, tempReg, dataReg);
GetEmitter()->emitIns_R_R_R(INS_ldclral, dataSize, tempReg, (targetReg == REG_NA) ? REG_ZR : targetReg, GetEmitter()->emitIns_R_R_R(INS_ldclral, dataSize, tempReg, targetReg, addrReg);
addrReg);
break; break;
} }
case GT_XCHG: case GT_XCHG:
@ -3908,8 +3910,7 @@ void CodeGen::genLockedInstructions(GenTreeOp* treeNode)
break; break;
} }
case GT_XADD: case GT_XADD:
GetEmitter()->emitIns_R_R_R(INS_ldaddal, dataSize, dataReg, (targetReg == REG_NA) ? REG_ZR : targetReg, GetEmitter()->emitIns_R_R_R(INS_ldaddal, dataSize, dataReg, targetReg, addrReg);
addrReg);
break; break;
default: default:
assert(!"Unexpected treeNode->gtOper"); assert(!"Unexpected treeNode->gtOper");

11
src/coreclr/jit/lsraarm64.cpp
View file

@ -1086,10 +1086,17 @@ int LinearScan::BuildNode(GenTree* tree)
} }
setInternalRegsDelayFree = true; setInternalRegsDelayFree = true;
} }
buildInternalRegisterUses();
if (dstCount == 1)
{
BuildDef(tree);
}
} }
buildInternalRegisterUses(); else
if (dstCount == 1)
{ {
// We always need the target reg for LSE, even if
// return value is unused, see genLockedInstructions
buildInternalRegisterUses();
BuildDef(tree); BuildDef(tree);
} }
} }