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JIT ARM64-SVE: Allow LCL_VARs to store as mask (#99608)

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* JIT ARM64-SVE: Allow LCL_VARs to store as mask

* Remove FEATURE_MASKED_SIMD

* More generic ifdefs

* Add varTypeIsSIMDOrMask

* Add extra type checks

* Fix use of isValidSimm9, and add extra uses

* Rename mask conversion functions to gtNewSimdConvert*

* Add OperIs functions

* Mark untested uses of mov

* Add INS_SCALABLE_OPTS_PREDICATE_DEST

* Valuenum fixes for tier 1

* Remove importer changes

* XARCH versions of OperIsConvertMaskToVector

* Revert "Remove importer changes"

This reverts commit b5502a6968c1304986f206ea6ac9de9d2fb63f7d.

* Add tests fopr emitIns_S_R and emitIns_R_S

* Fix formatting

* Reapply "Remove importer changes"

This reverts commit d8dea0e83c2318a4638d9beea11d3d188c2d5fa2.

* Use dummy mask ldr and str

* Refactor emitIns_S_R and emitIns_R_S

* Move str_mask/ldr_mask

* Fix formatting

* Set imm

* fix assert

* Fix assert (2)

* Fix assert (3)

* nop
This commit is contained in:
Alan Hayward 2024-03-21 16:38:45 +00:00 • committed by GitHub
parent effc9e5d92
commit 12d96ccfae
Signed by: github
GPG key ID: B5690EEEBB952194
16 changed files with 317 additions and 137 deletions
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3
src/coreclr/jit/valuenum.cpp
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@ -12092,9 +12092,6 @@ void Compiler::fgValueNumberHWIntrinsic(GenTreeHWIntrinsic* tree)
// There are some HWINTRINSICS operations that have zero args, i.e. NI_Vector128_Zero
if (opCount == 0)
{
// Currently we don't have intrinsics with variable number of args with a parameter-less option.
assert(!isVariableNumArgs);
if (encodeResultType)
{
// There are zero arg HWINTRINSICS operations that encode the result type, i.e. Vector128_AllBitSet